// -*- mode:c++ -*-

// Copyright (c) 2010-2013 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

let {{
    vfpEnabledCheckCode = '''
        uint32_t issEnCheck;
        bool trapEnCheck;
        uint32_t seq;
        if (!vfpNeonEnabled(seq,Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck,
                            trapEnCheck, xc->tcBase(), Fpexc))
            {return disabledFault();}
        if (trapEnCheck) {
            CPSR cpsrEnCheck = Cpsr;
            if (cpsrEnCheck.mode == MODE_HYP) {
                return std::make_shared<UndefinedInstruction>(
                                                machInst, issEnCheck,
                                                EC_TRAPPED_HCPTR, mnemonic);
            } else {
                if (!inSecureState(Scr, Cpsr)) {
                    return std::make_shared<HypervisorTrap>(
                                              machInst, issEnCheck,
                                              EC_TRAPPED_HCPTR);
                }
            }
        }
    '''

    vfp64EnabledCheckCode = '''
        CPSR cpsrEnCheck = Cpsr;
        ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsrEnCheck.el;
        if (!vfpNeon64Enabled(Cpacr64, el))
             return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
                                       EC_TRAPPED_SIMD_FP);

        if (ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) {
            HCPTR cptrEnCheck = xc->tcBase()->readMiscReg(MISCREG_CPTR_EL2);
            if (cptrEnCheck.tfp)
                return std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
                                          EC_TRAPPED_SIMD_FP);
        }

        if (ArmSystem::haveSecurity(xc->tcBase())) {
            HCPTR cptrEnCheck = xc->tcBase()->readMiscReg(MISCREG_CPTR_EL3);
            if (cptrEnCheck.tfp)
                return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
                                             EC_TRAPPED_SIMD_FP);
        }
    '''

    vmsrEnabledCheckCode = '''
        uint32_t issEnCheck;
        bool trapEnCheck;
        uint32_t seq;
        if (!vfpNeonEnabled(seq,Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck,
                            trapEnCheck, xc->tcBase()))
            if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID)
                {return disabledFault();}
        if (!inPrivilegedMode(Cpsr))
            if (dest != (int)MISCREG_FPSCR)
                return disabledFault();
        if (trapEnCheck) {
            CPSR cpsrEnCheck = Cpsr;
            if (cpsrEnCheck.mode == MODE_HYP) {
                return std::make_shared<UndefinedInstruction>(
                                                machInst, issEnCheck,
                                                EC_TRAPPED_HCPTR, mnemonic);
            } else {
                if (!inSecureState(Scr, Cpsr)) {
                    return std::make_shared<HypervisorTrap>(
                                              machInst, issEnCheck,
                                              EC_TRAPPED_HCPTR);
                }
            }
        }
    '''

    vmrsEnabledCheckCode = '''
        uint32_t issEnCheck;
        bool trapEnCheck;
        uint32_t seq;
        if (!vfpNeonEnabled(seq,Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck,
                            trapEnCheck, xc->tcBase()))
            if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID &&
                op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1)
                {return disabledFault();}
        if (!inPrivilegedMode(Cpsr))
            if (op1 != (int)MISCREG_FPSCR)
                return disabledFault();
        if (trapEnCheck) {
            CPSR cpsrEnCheck = Cpsr;
            if (cpsrEnCheck.mode == MODE_HYP) {
                return std::make_shared<UndefinedInstruction>(
                                                machInst, issEnCheck,
                                                EC_TRAPPED_HCPTR, mnemonic);
            } else {
                if (!inSecureState(Scr, Cpsr)) {
                    return std::make_shared<HypervisorTrap>(
                                              machInst, issEnCheck,
                                              EC_TRAPPED_HCPTR);
                }
            }
        }
    '''
    vmrsApsrEnabledCheckCode = '''
        uint32_t issEnCheck;
        bool trapEnCheck;
        uint32_t seq;
        if (!vfpNeonEnabled(seq,Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck,
                            trapEnCheck, xc->tcBase()))
            {return disabledFault();}
        if (trapEnCheck) {
            CPSR cpsrEnCheck = Cpsr;
            if (cpsrEnCheck.mode == MODE_HYP) {
                return std::make_shared<UndefinedInstruction>(
                                                machInst, issEnCheck,
                                                EC_TRAPPED_HCPTR, mnemonic);
            } else {
                if (!inSecureState(Scr, Cpsr)) {
                    return std::make_shared<HypervisorTrap>(
                                              machInst, issEnCheck,
                                              EC_TRAPPED_HCPTR);
                }
            }
        }
    '''
}};

def template FpRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest, IntRegIndex _op1,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _op1, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _imm, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          uint64_t _imm,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};
